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PCAN-USB Pro FD - Firmware Version History

2025-05-28 - Version 3.5.3

  • GUID support added

PEAK-Flash tool with embedded firmware file

2024-04-18 - Version 3.4.7

Bug fixes:

  • SOF and OUT-NACK IRQs disabled due to IRQ flooding on OUT-PINGs
  • 2nd device ID was not returned by vendor request (available on Linux)

2022-03-28 - Version 3.4.4

  • CAN Core updated
  • Option added: Send ACK as transmitter
  • Option added: Generate time stamp at start of frame
  • Option added: Ignore BRS frames as receiver
  • LIN commands improvements
  • LIN Wake-Up was not working after LIN power cycles
  • Bugfix: Status Frame suppressed when leaving reset mode during BusOff
  • Internal Firmware improvements

2017-08-31 - Version 3.2.0

  • Bugfix for CAN bitrate prescaler
  • Mode added to force CAN 2.0 A/B
  • Timestamps for RCV frames at bit 6 of end-of-frame

Version 3.1.1

  • Bugfix CAN core, bad TX data due to RAM pointer increment
  • TX pause added for transmit delay

Version 3.1.0

  • Bugfix CAN core, bad TX data due to RAM pointer reset

Version 3.0.0

  • New CAN core Gen 3 included (new implementation of BSP/BTL, tested with Bosch Ref CAN model)

Version 2.3.1

  • Bugfix/modification for timestamp system (CAN/LIN with offset)

Version 2.3.0

  • Firmware version change for USB MSD bootloader

Version 2.2.1

  • Bugfix: bad frames in CAN FD ISO mode with DLC=0

Version 2.2.0

  • Bugfix "error frames in listen-only mode"
  • USB descriptor for LIN endpoints modified
  • USB "other descriptor" modified

Version 2.1.0

  • Modification USB suspend
  • Fast-forward option added

Version 2.0.3

  • Flash mode depends on password
  • LED toggle for locked CAN

Version 2.0.2

  • CAN BusOff issue fixed

Version 2.0.1

  • USB suspend reactivated

Version 2.0.0

  • CAN core with ISO/Non-ISO support
  • OEM area added (OEM_CODE, password ...)

Version 1.1.6

  • Modification for USB packet sizes of LIN endpoints (limited FIFO size of USB controller, data corruption on parallel CAN/LIN communication)

Version 1.1.5

  • FPGA modification for I/O signaling